The application of hysteresis to the inputs of an integrated circuit chip is commonly used to provide transition noise immunity to a system. Prior art CMOS inputs typically have (1) a first trip point for which a value of voltage of an input voltage signal above the value of the first trip point causes a corresponding output voltage signal to transition from a “low” level to a “high” level and (2) a second trip point for which a value of voltage of an input voltage signal below the value of the second trip point causes a corresponding output voltage signal to transition from a “high” level to a “low” level.
This means that for a standard prior art CMOS input, if the input voltage is noisy (or if the power and ground on the input of the chip are noisy) the input may be seen to transition more than once as it goes from a “high” level to a low “level” or from a “low” level to a “high” level. These transitions are referred to as transition noise.
It is well known that a hysteresis circuit may be used counteract the effects of transition noise. FIG. 1 illustrates an exemplary plot 100 of an input voltage signal 110 and an output voltage signal 120 of a prior art hysteresis circuit over time (where the time is measured in nanoseconds). The input voltage signal 110 rises from a value of zero volts (0.0 volts) at time zero (On) to a value of three volts (3.0 volts) at two hundred nanoseconds (200 n). The input voltage signal 110 then drops from a value of three volts (3.0 volts) at two hundred nanoseconds (200 n) to a value of zero volts (0.0 volts) at four hundred nanoseconds (400 n).
In response the output signal voltage 120 rises from a value of zero volts (0.0 volts) to three volts (3.0 volts) at approximately one hundred twenty five nanoseconds (125 n). The output signal voltage 120 then remains at three volts (3.0 volts) until approximately three hundred fifteen nanoseconds (315 n). At that point the value of output signal voltage 120 drops to a value of zero volts (0.0 volts).
The first trip point for input signal voltage 110 that causes a transition of output voltage signal 120 from a “low” level to a “high” level occurs at voltage level VA. That is, when the input voltage signal 110 is rising then the input voltage signal 110 must reach the value of voltage VA in order to trigger a transition of output voltage signal 120 from a “low” level to a “high” level.
The second trip point for input signal voltage 110 that causes a transition of output voltage signal 120 from a “high” level to a “low” level occurs at voltage level VB. That is, when the input voltage signal 110 is falling then the input voltage signal 110 must reach the value of voltage VB in order to trigger a transition of output voltage signal 120 from a “high” level to a “low” level.
The actual values of voltage VA and of voltage VB may be varied by adjusting the hysteresis input circuit. The voltage range between voltage VA and voltage VB is referred to as the “dead zone”. The amount of hysteresis is the voltage difference VA–VB. In the “dead zone” changes in the value of input voltage signal 110 do not affect the value of output voltage signal 120.
For example, as previously mentioned, if input voltage signal 110 is rising it must reach the voltage value VA in order to trigger a transition of output voltage signal 120 from a “low” level to a “high” level. After the transition of output signal voltage 120 from “low” to “high” has occurred, if there is noise on the input voltage signal 110 then the noise on input voltage signal 110 must be equal to or greater than the amount of hysteresis VA–VB before the output signal voltage 120 would change from its “high” level to a “low” level. That is, the addition of noise to the input voltage signal 110 would have to cause input voltage signal 110 to fall below the voltage level VB. This means that the noise immunity is given by the voltage difference VA–VB.
Similarly, if input voltage signal 110 is falling it must reach the voltage value VB in order to trigger a transition of output voltage signal 120 from a “high” level to a “low” level. After the transition of output signal voltage 120 from “high” to “low” has occurred, if there is noise on the input voltage signal 110 then the noise on input voltage signal 110 must be equal to or greater than the amount of hysteresis VA–VB before the output signal voltage 120 would change from its “low” level to a “high” level. That is, the addition of noise to the input signal voltage signal 110 would have to cause input signal voltage 110 to rise above the voltage level VA. Once again, the noise immunity is the voltage difference VA–VB.
FIG. 2 illustrates an exemplary prior art hysteresis input circuit 200. Prior art hysteresis circuits typically work by using contention between the power voltage (VDD) and the ground voltage (VSS). Although the contention method may be easily used to implement hysteresis, the contention between the power voltage (VDD) and the ground voltage (VSS) is wasteful of current. Further, in integrated circuit chips that have large numbers of inputs the contention method may contribute to glitching of the power level and the ground level inside the integrated circuit chip.
Prior art hysteresis input circuit 200 illustrated in FIG. 2 comprises six metal oxide semiconductor field effect transistors (MOSFET). Transistor 210 (designated P1), transistor 220 (designated P2) and transistor 230 (designated P3) each comprise a p-channel transistor. Transistor 240 (designated N1), transistor 250 (designated N2) and transistor 260 (designated N3) each comprise an n-channel transistor.
The input signal (designated PAD_IN) to hysteresis input circuit 200 is applied to the gate of each of the transistors 210 (P1), 220 (P2), 240 (N1) and 250 (N2). As shown in FIG. 2 node INZ is located between transistor 220 (P2) and transistor 240 (N1). The gate of transistor 230 (P3) is coupled to node INZ. The gate of transistor 260 (N3) is also coupled to the node INZ.
Consider the operation of hysteresis input circuit 200 when the input signal voltage PAD_IN transitions from “low” to “high”. The value of the input signal voltage PAD_IN is initially zero and the value of voltage at node INZ is equal to the power voltage VDD. When this occurs then transistor 260 (N3) is completely on. As the value of input signal voltage PAD_IN rises the value of voltage will eventually reach the threshold voltage value Vth. A typical value of Vth is in the range from five tenths volt (0.5 volt) to nine tenths volt (0.9 volt).
When the value of the PAD_IN input signal reaches the value of the threshold voltage Vth, then transistor 240 (N1) and transistor 250 (N2) begin to turn on. Transistor 250 (N2) sinks the current that is provided by transistor 260 (N3), thereby hampering the ability of transistor 260 (N3) to pull down node INZ. As the value of the PAD_IN input signal continues to rise, at some point transistor 250 (N2) is able to overcome the current that is provided by transistor 260 (N3), and voltage value at node INZ begins to drop. As the voltage value at node INZ drops, transistor 260 (N3) is debiased (that is, the gate to source voltage Vgs of transistor 260 (N3) decreases) until transistor 240 (N1) and transistor 250 (N2) are able to pull the value of voltage at node INZ to ground, at which time transistor 260 (N3) is fully off. During this transition transistor 260 (N3) and transistor 250 (N2) are sinking current from VDD to ground VSS.
Now consider the operation of hysteresis input circuit 200 when the input signal voltage PAD_IN transitions from “high” to “low”. The value of the input signal voltage PAD_IN is initially equal to the power voltage VDD and the value of voltage at node INZ is equal to the ground voltage VSS. When this occurs then transistor 230 (P3) is completely on. As the value of the input signal voltage PAD_IN decreases the value of PAD_IN will eventually reach a value of voltage for which the sum of PAD_IN and the threshold voltage Vth will be approximately equal to the power voltage VDD. When this occurs (i.e., when PAD_IN+1 Vth≅VDD), transistor 210 (P1) will be turned on. At this time transistor 230 (P3) will be fully on, so the current flow from transistor 210 (P1) will be sunk to ground rather than causing node INZ to transition to a high. As PAD_IN input signal continues to decrease in value, the gate to source voltage Vgs across transistor 210 (P1) increases until transistor 210 (P1) overpowers transistor 230 (P3), and the voltage level at node INZ begins to rise. As the voltage level at node INZ begins to rise, transistor 230 (P3) becomes debiased, and transistor 210 (P1) and transistor 220 (P2) drive the voltage at node INZ to the VDD voltage level. The action of hysteresis input circuit 200 is based upon sinking current from VDD to ground VSS.
The function that is performed by hysteresis input circuit 200 may also be performed using other types of circuits. For example, it would be possible to operate hysteresis input circuit 200 even if transistor 230 (P3) or transistor 260 (N3) (but not both) were deleted.
The prior art approach discussed above is inefficient because it generates significant levels of transient response current. The contention between the power voltage (VDD) and the ground voltage (VSS) wastes current. Therefore, there is a need in the art for a more efficient system and method for providing hysteresis for reducing transition noise in the inputs to an integrated circuit chip.